ISL6112INZA-T【PDF 23/30 页】IC PWR CNTRLR DUAL SLT 48-TQFP

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Sheet目录38

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ISL6112

FN6456.1

August 25, 2011

Control Register, Slot B (CNTRLB) 8-Bits, Read/Write

Power-Up Default Value:

0000 0000

= 00

Command_Byte Value (R/W):

0000 0100

= 04

The power-up default value is 00

. Both slots are disabled upon power-up; i.e., all supply outputs are off. In response to an overcurrent fault condition,

writing a Logical 1 back into the active (or set) bit position will clear the bit and deassert INT

. The status of the FAULT

A pin is not affected by reading

the Status Register or by clearing active status bits.

NOTES:

10. If FAULTA has been set by an overcurrent condition on one or more of the MAIN outputs, the ONA input must go LOW to reset FAULTA. If FAULTA has

been set by a VAUXA overcurrent event, the AUXENA input must go LOW to reset FAULTA. If an overcurrent has occurred on both a MAIN output and

the VAUX output of slot A, both ONA and AUXENA of the slot must go low to reset FAULTA.

11. Neither the FAULTA bits nor the FAULT

A pins are active when the ISL6112 power paths are controlled by SMI. When using SMI power path control,

AUXENA and ONA pins for that slot must be tied to GND.

12. If FORCE_ON

A is asserted (low), the FAULT

A pin will be unconditionally forced to its open-drain state. Note that the value in the FAULTA register bit

is not affected by FORCE_ON

A. It will instead continue to read as a high if no faults are present on Slot A, and as a low if any fault conditions exist

that would disable Slot A if FORCE_ON

A was not asserted.

TABLE 7. CONTROL REGISTER, SLOT B (CNTRLB)

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1] D[0]

read-only

read/write read/write read/write

AUXBPG

MAINBPG

Reserved

FORCE

ENABLE

MAINB VAUXB

BIT(s)

FUNCTION

OPERATION

BIT(s)

FUNCTION

OPERATION

AUXBPG AUX output power-good status, Slot B

1 = Power-is-Good (VAUXB Output is above its UVLO threshold)

MAINBPG MAIN output power-good status, Slot B

1 = Power-is-Good (MAINB Outputs are above their UVLO

thresholds)

D[5] Reserved

Always read as zero

D[4] Reserved

Always read as zero

D[3] Reserved

Always read as zero

FORCE

ENABLE

Allows or inhibits the operation of the FORCE_ON

B input pin

0 = FORCE_ON

B is enabled

1 = FORCE_ON

B is disabled

MAINB MAIN enable control, Slot B

0 = OFF, 1 = ON

VAUXB VAUX enable control, Slot B

0 = OFF, 1 = ON

Power-Up Default Value:

0000 0000

= 00

Command_Byte Value (R/W):

0000 0011

= 03

The power-up default value is 00

. Slot is disabled upon power-up; i.e., all supply outputs are off.

NOTES:

13. The state of the PWRGD

B pin is the logical AND of the values of the AUXBPG and MAINBPG bits, except when FORCE_ON

B is asserted. If

FORCE_ON

B is asserted (the pin is pulled low), and FORCE

_BENABLE is set to a logic zero, the PWRGD

B pin will be unconditionally forced to its

open-drain (Power Not Good) state.

14. The values of the MAINBPG and AUXBPG register bits are not affected by FORCE_ON

B, but will instead continue to read as high if power is Good,

and as low if the conditions, which indicate that power is good, are not met.

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